module PC(
        input CLK,
        input RST,
        input PCWr,
        input [31:0] D,
        output reg[31:0] Q
    );
    initial begin
        Q=0;
    end
    always @(posedge CLK) begin
        if(RST) begin
            Q<=0;
        end
        else
            if(PCWr)
                Q<=D;
    end
endmodule
